• Nominal Analog Bandwidth @ 50Ω, 10mV-1V/div: 1GHz (≥2mV/div)
• Risetime (10 to 90%): 375ps typical
• Risetime (20 to 80%): 280ps typical
• Input Channels: four
• Bandwidth Limiters: 20MHz, 200MHz
• Input Impedance: 50Ω ±2% or 1MΩ, 17pF; 10MΩ, 9.5pF with supplied Probe
• Maximum Input Voltage, 50Ω: 5VRMS ±10V peak
• Maximum Input Voltage, 1MΩ: 400V (DC+ peak AC <10kHz)
• Channel-Channel Isolation: >100:1 up to rated BW
• Vertical Resolution: 8 bits; up to 11 bits with enhanced resolution (ERES)
• Sensitivity, 50Ω: 1mV/div to 1V/div, fully variable
• Sensitivity, 1MΩ: 2mV/div to 10V/div, fully variable
• DC Vertical Gain Accuracy (gain component of DC accuracy): ±1% F.S. typical, offset at 0V; ±1.5% (test limit), offset at 0V
• Offset Range, 50Ω, 2mV to 4.95mV: ±1.6V
• Offset Range, 50Ω, 5mV to 9.9mV: ±4V
• Offset Range, 50Ω, 10mV to 19.8mV: ±8V
• Offset Range, 50Ω, 20mV to 1V: ±10V
• Offset Range, 1MΩ, 2mV to 4.95mV: ±1.6V
• Offset Range, 1MΩ, 5mV to 9.9mV: ±4V
• Offset Range, 1MΩ, 10mV to 19.8mV: ±8V
• Offset Range, 1MΩ, 20mV to 140mV: ±16V
• Offset Range, 1MΩ, 142mV to 1.4mV: ±80V
• Offset Range, 1MΩ, 1.42mV to 10V: ±160V
• DC Vertical Offset Accuracy: ±(1.5% of offset setting +1% of full scale +1 mV)(test limit)

Horizontal System

• Clock Accuracy: ≤1.5ppm +(aging of 0.5 ppm/yr from last calibration)
• Trigger and Interpolator Jitter: ≤3.5ps rms typical; <0.1 ps rms (typical, software assisted)
• External Clock: DC to 100MHz; (50Ω/1MΩ), EXT BNC input. Minimum rise time and amplitude requirements apply at low frequencies.

Acquisition System

• Single-Shot Sample Rate/Ch: 10GS/s on 4-channel, 20GS/s on 2-channel
• Memory Options (4-Ch/2-Ch/1Ch), S-32 Option: 32M/64M/64M (15,000)
• Memory Options (4-Ch/2-Ch/1Ch), M-64 Option: 64M/128M/128M (15,000)
• Standard Memory (4-Ch/2-Ch/1Ch)(Number of Segments): 16M/32M/32M (4500)

Acquisition Processing

• Enhanced Resolution (ERES): From 8.5 to 11 bits vertical resolution

Triggering System

• Trigger Sensitivity with Edge Trigger (Ch 1-4) ProBus Inputs: 2 div @ <1GHz; 1.5 div @ <500MHz; 1 div @ <200MHz; 0.9 div @ <10MHz (DC, AC, and LFRej coupling, ≥10mV/div, 50Ω)
• External Trigger Sensitivity, Edge Trigger: 2 div @ 1GHz; 1.5 div @ <500MHz; 1 div @ <200MHz; 0.9 div @ <10MHz (DC, AC, and LFRej coupling)
• Max. Trigger Frequency, SMART Trigger: 1.0GHz @ ≥10mV/div (minimum triggerable width 750ps)

High Speed Serial Protocol Triggering

• Data Rates: 320Mb/s to 3Gb/s
• Pattern Length: 80 bits, NRZ or 8b10b
• Clock Recovery Jitter: 1ps rms + 0.3% Unit Interval rms for PRBS data patterns with 50% transition density
• Hardware Clock Recovery Loop BW: PLL Loop BW = Fbaud/5500, 100Mb/s to 2.488Gb/s (typical)

LeCroy WaveStream™ Fast Viewing Mode

• Max Sampling Rate: 10GS/s (20GS/s when interleaved)

Auxiliary Input

• Max. Input Voltage: 50Ω: 5Vrms; 1MΩ: 250Vmax (DC + Peak AC ≤10kHz)